:- ,. analog w devices i features ultra fast 10ns settling time to 0.2% (hdd-0810) 15ns settling time to 0..1% (hdd-1015) internal monolithic reference low 200pv-sec glitch energy single -5.2v power supply available screened to mi l.std-883 designed for general output compatibility with eia standards rs-170 and r5-343, including 10% brightnell complete composite inputs (hdd-081oc, hdd-1015c) appuca tions raiter scan and vector graphic displays tv video reconstruction . ultra fast current or voltage output dac for use in analyticellnstrumentati.on digital vcos general description the hdd-08l0 and hod-lots combine state-of-the-art tech- nology with the latest active laser trimming techniques to achieve the world's fastest 8- and to-bit voltage output dlgital- to-analog converters of their type. containing input registers and an ultra stable monolithic in- ternal reference, the hdd-08l0 8-bit d/a converter settles to within 0.2% in ions, while the la-bit version hdd-lots set- . ties to within 0.1 % in only lsns. they arc; compatible with standard ecl logic levels. the 7 sa output impedance allows them to drive 7sa cables or filters directly, without costly external output drivers. this feature assures that a full one volt is available at the load, since the'd/ a output is a mini- mum of 27ma (hdd-lols). additionally, these d/as are monotonic over the full operating temperature range of -2soc to +8soc (metal case versions), or 0 to +70c for the com- mercial style glass-ceramic package, and require only a single .,.s.2v supply for operation. the hdd-08loc and hdd-lolsc combine all of the above features with full composite input capability. which allows operation directly with raster scan/output video display sys- tems, these controls include composite sypc, blanking, setup and a 10% brightness input which gives the user digital control of the picture's intensity. further, the hdd series d/a con- verters contain provisions for externai adjustments to optimize differential phase and gain, critical considerations in composite color video applications. ." - -- hybrid video low glitch d/a converter hod series i hdd series functional block diagram comi'osite svnc @ deglitch bit 1 if' ~: deglitch bit 2 ~ ' deglitch bit 3 . reference 21 white current switch '0' ".'mus. ecl register output d' eo 20' '51' output current controlled bv digital input cool . ground strob. ~ reference ~ blck composite blanking . "'" bright current switch 1.0 141 ... ~ !it- 0.8 ... ... ::i ... ... 0.6 0 111 i ~ 0.4 ~ a; ::i u ~ 0.2 0.1 0.05 5 10 15 20 settling time - nl time is measured from 50% transition point of the strobe with input data lines qeskewed and 71id load. voltage output. inherent delay of internal register (3m! has been disregarded. 0 25 hod series d/a converters accuracy vb. settling time -- , - \ \ 1'- - obsolete
~pecifica tions - (typical @ +25cwith nominal power supplies and 75n output load unless othe~ise noted) model units hdd-o81 0 hdd-o81oc hdi>10ls hdi>1015c resolution fs.. full scale bits 8 8 10 10 lsb weight (current) ila' 106 67 27 17 lsb weight (voltage) mv 4 2.5 1 0.625 accuracy. :t% of fs 0.1 o.os :t% of gs 0.1 *ita "26.5 ' 17 guaranteed - . -1.4 . linearity monotonicity zero offset (initial) temperature coefficients linearity zero offset gain strobe input logic compatibility logic voltage levels "i" ",' (positive logic) "0" .. logic loading set-up time (data) hold time (data) propagation delay reference black and reference white inputs2 logic compatibility logic voltage levels "i" = "0"", logic loading data inputs logic compatibility logic voltage levels "i" '" (positive logic) "0" = logic loading (each bit) coding (see table) composite sync input logic compatibility logic voltage levels "1" '" "0"= logic loading for logic "i" lolic "0" composite blanking and 10% bright inpjjts logic compatibility logic voltage levels "1" "0" logic loading setup control ground open -~ 'jv output3 current , voltage4 compliance intemallmpedance output - composite sync current volt3l!e output - 10% bright current voltage output - composite blankings current v2wic mv ppmfc ppmfc efmfc v v ns ns ns v v v v v v v v mv mv mjl. ma' v (:tl%) v r1(:ts%) ma (:ts%) mv (:t5%) ma (:t5%) mv (:t5%) ma (:tl %) mv (:tl%) 5 1 80 ecl -0.9 -1.7 5opf and 5kr1 to -5.2v 2.5 min 1.5 min 3 see note 2 ecl -0.9 -1.7 5opf and 5kr1 ~. ecl -0.9 -1.7 5pf and 50kr1 to -5.2v. complementaty binaty (cbn) n/a n/a n/a n/a n/a n/a n/a n/a !:ua 0 (0 ire units) 71 (10 ire units) 142 (20 ire units) 0 to -27.2 0 to -1.020 +1.1 to -1.1 75 n/a n/a n/a n/a n/a n/a vol. 1,9-296 oigital-td-analog converters 13 .. . " . . . . . . . . " . . . . . . . . . . . . . . . . sopf and skr1' 5pf and'sokr1 . . . 5pf and 50kr1 . . .. . . . . . . ecl -0.9 -1.7 5pf, +7.6ma 5ff, -50p.a n/a n/a n/a n/a n/a ecl -0.9 -1.7 5pf and 50kr1 ~ n/a n/a n/a ~ . . . . . oto-17 0 to -0.6375 . 0 to -27.3 0 to -1.023 . . 0 or -7.6 0 or -286 n/a n/a 0 or -1.9 0 or -71 n/a n/a 0,-17.0, -18.9, or-20.8 0,-637.5,-708.75 or-780 n/a n/a o.os 8.5 . . . . . . . . . . . . . ecl -0.9 -1.7 spf, +7.6ma 5ff, -501la ecl -0.9 -1.7 5pf and 50kr1 12..:.1.2y 0 to -17.05 oto-0.63937s . 0 or -7.6 0 or -286 00r-1.9 00r-7.1 o,-17.0s, -18.95, or-20.85 . 0, -639.4, -710.6, or-781.9 ~ obsolete
model speed performance - full scale or gray scale output settling time (voltage)6 slew rate update rate 7 rise time g,litch energy' speed performance - control inputs settling time to 10% of final value for: composite sync composite blanking reference white reference black 10% bright power requirements -s.2v:!:0.2sv , power supply sensitivity reference temperature range operating, glass case operating, metal case". ("m") storage mtbf9 mean time between failure package options1o notes i accuracy ;s relative to full scale (fs) for binary versions, or reladve to sray scale (gs) for composite ("c") versions, and includes linearity, . reference white on models hdd-osi0, -1015 a logic "i" on pin 30 reference black will produce all "0" code 0 volta output; a lope "i" on pin 29 reference white will produce all "1" code:"1 volt output. on models hdd-osioc, 10bc a lope "0" on pin 30 reference mack will produce all "i" code 0 volta output; a lope "0" on pill 29 reference white will produce all "0" code -1 volt output. . 'the output is shown for full scale (f5) for binaty versions, and for full jray scale (gs>' for composite (~'c") versions.' 'the difference between the full-scale output of 631.5mv and 643mv shown elsewhere herein is due to the fact that we selected an lsb value of 2.5m v for eue of calibration. these differences are well within the output .nd eia standard rs-i10 tolerance.. 'the three currents and volt- correspond to the three set-up levels of 0, 10, and 20 ire units as extemally selected. .wont case settling time includes fs and most significant bit (msb) transition.. the inherent 3ns proposition delay throuab the input registers .(50% point of strobe to 50% point of register output) has been disregarded. settling time to a percentage of fs is given for straight versions, and settling time to a percentage of maximum jray scale (gs) is given for composite video output ("c") venion.. 'the update rates shown are limited by a full scale settling time that is uaeabje for the number of bits of resolution. both dacs may be operated up to 125mhz with settling time degradation. this is the limit of the lope switching speed. . reducible to less than l00pv-s with appropriate deskewing of dqptal inputs. see applications section.. 'calculated for hdd-i015cmb usm, mil handbook 211. ground: fixed tempentun: case. 6o"c. 10 see section 19 for packap outlide information; .specifications same as for hdd-osi0. specifications subject to change without notice. c case c case c 0 to +10 -2s to +8s -ss to + 12s . . hours i >300,000 hy32a hy32c pin designations ordering note 1. to order devices with hennetically sealed metal cases, add "m" suffix to part number; example: hdd-o810cmb on the hdo~10 and hdc>4il0 and hoo.l011, pins 21, 77. and a all. not used. all ground pins (i. ii, 11-22; 3>1 are connected internally. --- -- -~-- units hdd-o810 hdd-o81oc ood-i015 hdd-i015c ns (t % fs) 10 (0.2) is (0.1) or(to%gs) 10(0.2) is (0.1) vlp.s 200 . . . mhz 100 100 - 67 67 ns 4 . . . pv-s i 200 . . . ns n/a 10 n/a 10 ns n/a 10 n/a 10 ns n/a 10 n/a 10 ns n/a 10 n/a 10 ns n/a 10 n/a 10 ma' 380 390 4s0 4s0 %1% 0.04/1 . . monolithic, internal . pin function i g- 2 deollfch 8it 1 3 8itii-, .. alt2 5 _itch alt 2 . . deglltch lit 3 7 lit 3 . lit" . 8111 10 sfr081 ii .it. 12 8it7 13 iits 14 lit i 1& alt 10 lull 18 giiouno 17 -8.2y ii ground ii ground 20 ground 21 ground 22 giiouno 23 output 20 glitch aoiuit 211 teiync a utiii' 77 cowoiite iunkinq 211 "" aright 2t referenca white 30 referenelllaell 31 giiouno :12 -8.2y obsolete
at't'lll.ailons in.'ormation ~ high-speed low-glitch-opera tion suggestions the hd~ series d/as offer the highest available speed. how-. ever, with this speed performance, certain precautions and operation conditions should be considered. 1. the di a converter !;hould be provided with a very low impedance grounding system to very high frequencies. a large ground plane is a must. 2. low frequency bypassing should be provided with a 11jf (or larger) tantalum capacitor mounted between the -5.2v supply line and ground near the di a. 3. high frequency bypassing should be provided by cerami<; capl!.citors of o.l1jf or larger mounted 'vithin 0.25 inches of pins 17 and 32 to ground (see figure 1). 4. the threshold of the internal current switches can be opti- mized for low glitch energy by the addition of an external potentiometer connected to pin 24 of the d/a (see fig- ure 1). this potentiometer is adjusted for minimum glitch energy as shown in photo 2. if required, variable capacitors can be added tp "deskew" the most significant bits for lowest glitch-although this is not usually required in many applications. these capaci- tors are added as shown in figure t (c1-3). they are ad- justed in conjunction with the glitch adjust pot for mini- mum glitch energy as shown in photo'2.- in composite television applications, c1-3 are adjusted for best differential phase performance, and the glitch adjust is adjusted for best differential gain performance. these may tend to interact, so going back and forth between, adjustments maybe required. 5. standard 32-pin sockets should be avoided. individual "pin sockets" are most suited for evaluating devices, as lead inductance is reduced. in final designs, the d/as should be soldered directly into the printed cir~uit board without sockets. gain adjustment the hdd series d/as are actively laser-trimmed to provide a voltage into exactly 750. which is an even binary multiple; i.e., the hdd-os10 has an lsb of 4mv and the hdd-1015 - has an lsb of 1mv, this makes the full-scale output slightly greater than one volt. if an outputof exactly one volt is re- quired-such as for tv reconstruction-a 2k potentiometer may be placed across the output of the d/a for gain adjust- ment. for a one volt output, the adjusted value of this pot will be about 15000. (see figures 1 and 5). vol. " 9-298 digital-to-analog converters oeglitch bit i it hdd.gawc 01 hdd.w1sc oeglitch b't 2 oeglitch bit 2 c3 20 b't , imsbi r2 b" 2 r3 bit> ro b'" ro bits r6 . bito " r7 12 bit 7 ri 13 bito ri i< b'n r'~ .. bit ,. r11 '0 itrq8e reperence wh'te reference olack compos'te ivnc . composite blanking .. .. ri< .. "'0 27 too. br'ght .. notes ci.er'e """". ..-, lor eauivi -uv c2. c"er'e """'0. 1.32p' or eouiv c60"""" tantalum co. cboo.i.' ceramic ri-ri0. r12-ri"2k "ow.'" 1.11.18-22,31 figure 1. hdd-o810, hdd-1015c typical hook-up circuit ultra-low glitch operation for extremely low glitch requirements ?so - 100pv-s), an . hts-o025 track-and-hold is recommended as a deglitcher (see' . figure 2). the duutionof the hdd series d/a glitch is ap- proximately 10ns. the hold time of the hts-o025 should be at least 15ns to "mask out" the glitch. the minimum acqui- sition time oithe hts-o025 for 0.1% accuracy is 30ns. this implies that the circuit of figure 2 can be operated up to , 22mhz and still maintain to-bit accuracy. far 0.2% accuracy, the acquisition time for the t&h can be reduced to 25ns, allowing the circuit to operate to 25mhz: this discussion assumes that the d/a will be required to slew full scale (one volt) 'between adjacent samples. in practice, the sample-to- sample variation is less than full scale.depending on the amount of oversampling. in a practical situation, therefore, to-bit accuracy should be achievable at 25mh~ update rates. i. or 10.8" oigital 'nfut out ~ hts."" i output ii1 track and halo i2i 75 .a hold old -uv -5.2v ui . '0102 ecl '" clock input ~ lo holo tlm'ng track tin "' 0 20 50 70 figure 2. hts-oo25 track and hold used as a deglitcher (update ~ 2omhz) 4 23 output =-:r::: i i , i2kgainpot if reau'red 17 c6 32 --r:. obsolete
hdd-o81 ocihdd-1 015c characteristics of h.dd-iolsc (o810c] video dacs composite video signal 102412561 gray levels plus blanking and sync levels step size 0.625mv 12.smvi gray scale range 0.643v peak to peak setup control. "user programmable in three levels mv ire units definition of video terms blanking level the level separating the sync portion from the video portion of the waveform. usually referred to as the front porch of back porch. at 0 ire units, it is the level which will shut off the picture tube, resulting in the blackest possible picture. color video (rgb) this usually refers to the technique of combining the three primary colors of red, green, and blue to produce color pictures within the usual spectrum. in rgb moni- tors, three hdd "c" series pacs would be required, one for each color. composite sync signal (sync) the position of the composite video signal which syn- chronizes the scju1ning process. composite video signal the video signal with or without setup, plus the com- posite sync signal. gray scale the discrete levels of video signal between reference black and reference white levels. a 10-bit dac con" tains 1,024 different levels, while an 8-bit dac con- tains 256. 1. input grounded 0 2. input open 71 3. input @ -5.2v 142 reference white level ov absolute 100 ire units (+0. 714v relative to blanking level with standard setup; +0.643v relative to reference black) digital input for white level, all ones (1111111111) reference white/black controls\ overrides video input word" a logic 0 on pin 30 (reference black) will drive the output to reference black level of -643mv. a logic 0 on pin 29 (reference white) will drive the out- put to reference white level of 0 volts absolute. reference black level -0.643v absolute; +71'mv (10 ire units) relative to blanking level with standard setup. digital input for reference black all zeroes (0000000000) composite blanking level -0.714v absoluu., "(0 ire units) with standard setup. composite blanking input - pin 27\ ' logic 0 on pin 27 resets input register to 0000000000, and causes output voltage to go negative by the" amount of setup voltage with respect to the all "0" output voltage. composite sync level -1.0v absolute with standard setup. . -0.286v (-40 ire units) relative to blanking level (back porch). composite sync input - pin 25 logic 0 resets input register to 0000000000, and the" output voltage goes negative by 0.286v. 10% bright - pin 28 logic "0" causes output voltage to go positive by 71mv. strobe - pin 10 logic "0" to logic "i" transition clocks input register. 0 10 20 raster scan the most basic method of sweeping a crt one line at a time to generate and display images. this method is used in commercial television in the usa. reference black level the maximum negative polarity amplitude of the video signal. reference white level the maximum positive polarity amplitude of the video signal. setup the difference between the reference black level and the blanking level. this should"not be confused with setup as used with digital logic. " sync level the peak level of the composite sync signal. video signal " that portion of the composite video signal which varies in gray scal~ levels between refetence white, and refer- ence black. also referred to as the picture signal, this is the portion which may be visually observed. i note" i reference white (pin 29) should not be activated at the same rime aa composirc blankin8 (pin 27) or reference black (pin 30). 10% 8aighy level +10 -40 -1011mv sync level 11181 100 ire untn-1,4mv -~~~ ~~"'~""'-=-"'-"-.!"'--'="'f'~.~- i obsolete
deolltcm 8t' (2 output: o.2v/div reference white let current switches oimut cur"ent cont"olleo iv oioitai. iwut"""o 10' ito-27-- eo icl rioiiter 20 . .... strobe: o.5v/div rlat lino/di\! photo t. full scale rise time vs. strobe -6.2v flgum 4. hdd.tj8to:hdd-tot5 block diagram deolitch lit , -,-,oi ...~ diolitchi'u ~ r' i 124 _.- - ) ~~ ' lots)' ~ 112 . =~~::n':'f: 112 :::~ ~ i r output . ... iiti r ri' : ~ "" 11ft '- r" i , r' lit', 71 aoalni'dt lit' . ::" ~ if required 11ft'" ,. ri. lit'. "i i t7 tt"08e ~;;:::~ :~:;: ~ 'r -co '. '", '"-22.,,~ output: 2omv/div , , , , ; i . ' strobe: o.6v/div -6.2v lino/div notei c"irie_f",-f- c2.cs'e"'e~,""f co. ,oo.ft4ntalum ct.ci' o.'.f ceramic r,...'o.a diiit rt2. rts if "eference -,te and reference 8lack are not uted photo 2. midscale glitch hdd.()8toc, hdd-tot5c output waveform figure 5. hdd.osto, hdd-tot5 typical hook-up circuit analog output with 7s0 wad coding table vol. i, 9-300 digital- to-analog converters ~- ~ "", ",-~. '<:.~ - "'--~"'=-"--- ~ digital input hdd-o810 hdd-o810c hdd-lols hdd-lolsc 111...111 0 0 0 0 111...110 -4mv -2.smv -lmv -0.62smv 110 . . .000 -2s2mv -is7.smv -2ssmv -is9.37smv 101....111 -2s6mv' -16ornv -2s6mv -16ornv 100 . . . 111 -s08m v -317.smv -sl1mv -319.37smv 011.. .111 -s12mv -32ornv -si2mv -32ornv 010 . . . 000 -764mv -477.smv -767mv -479.37smv 001 . . . 111 -768q1v' -48orn v -768niv -48omv 000 . . . 001 -1016mv -63smv -1022mv -638.7smv 000 .. . 000 -102ornv -637.smv -1023mv -639.37smv obsolete
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